Interrupt controllers are used in microprocessors and microcontrollers to manage a plurality of possible interrupt sources and so-called exception handling. Interrupts generally cause an exception in the sequential processing of a program and the execution of an interrupt service routine (ISR) witch allows the processor to react to the respective interrupt source. However, entering and exiting an ISR takes time. An ISR usually requires certain “house cleaning” procedures before and after execution which are sometimes called preamble and post-amble. Such preamble or post-amble of the ISR are not interruptible. Hence, frequent but low priority interrupts can consume significant processor time by entering and exiting their ISR code. However, certain steps can be skipped in the ISR if there are multiple pending interrupts that are handled sequentially. Some systems use concepts as tail-chaining and others use concepts such as coalescing. Tail-chaining is a generic activity that can be applied to any interrupt system at the controller and ISR level. Tail-chaining reduces over head by skipping the restoring and saving of core registers when chaining to another ISR. Tail Chaining recognizes a pending interrupt while in the post-amble of an ISR, allowing the current ISR to skip restoring some state registers and all pushed general purpose registers (GPR). Tail Chaining also allows the ISR for the pending interrupt to skip storing the GPR state. Furthermore, it reduces the back-to-back interrupt handling by at least 2*GPR saved.
Coalescing is a specific activity that is applied to an interrupt source to limit the number of interrupts generated. Coalescing is simply counting a specific number of requests before an actual interrupt is asserted to the processor. Thus, coalescing delays assertion of an Interrupt Event until there are two or more interrupts to service for one interrupt source.